Computer Engineering CPE 487
- Bernard Yett from 2023 Fall to ???
- Darian Muresan from 2022 Fall to 2023 Spring
- In memory of Michel Ouendeno 1968—2022
- Kevin Lu from 2018 Fall to 2022 Spring
- Bryan Ackland from Fall 2011 to Spring 2018
- In memory of Stuart Tewksbury 1942—2013
- Learning
- SmartSim
- GHDL
- AMD Xilinx FPGAs
- Intel FPGAs
- TinyFPGA-BX
- Algorithms and data structures
- Audio and video
- Code
- Communications
- Digital signal processing
- Power and thermal management
- Projects
- Semiconductor
- Standards
- Tools
- A Symbolic Analysis of Relay and Switching Circuits 1938 by Claude Shannon 1916—2001
- Bit numbering
- Endianness refers to the order of bytes within a binary representation of a number in computing
- Danny Cohen 1937—2019
- A big-endian ordering places the most significant byte first and the least significant byte last, e.g., networking protocols such as Transmission Control Protocol (TCP)
- A little-endian ordering places the least significant byte first and the most significant byte last, e.g., processor architectures such as x86
- Binary-coded decimal (BCD)
- Ternary computer
- Ternary numeral system
- Trit (trinary digit)
- Tryte is defined as six trits
- Balanced ternary
- Three-valued logic
- Ternary numeral system
- IEEE 754 Standard for Floating-Point Arithmetic
- Floating point operations per second (FLOPS)
- Hexadecimal
- The prefix 0x denotes hexadecimal numerals, e.g., 0x2AF3 = 10 995
- Black box
- Boolean algebra
- Flip-flop
- Lookup table (LUT) - see hardware LUTs
- LUT as the basic building block of a field-programmable gate array
- Crystal oscillator
- Electronic oscillator
- Clock generator
- Clock signal
- Clock rate
- Double data rate (DDR)
- Quad data rate (QDR)
- Clock synchronization
- Synchronization in digital logic circuits
- Stanford University EE 183 Advanced Logic Design Laboratory
- Metastability
- Synchronization in digital logic circuits
- Turing machine by Alan Turing 1912—1954
- Finite-state machine (FSM)
- Mealy and Moore Machines by GeeksforGeeks
- Mealy vs. Moore machine overview video by Bruce Boatner
- The Moore-type outputs are only a function of the states and not the external inputs
- The Mealy-type outputs are a function of the states and the external inputs
- A hybrid FSM that contains both a Mealy and Moore-type output would be considered a Mealy-type FSM
- Moore machine by Edward Moore 1925—2003
- Have outputs defined inside their state bubbles
- Transition conditions listed on their transition arrows
- May seem a bit more intuitive in their notation
- May require more states than a Mealy machine
- Mealy machine by George Mealy 1927—2010
- Input and output variables listed on transition arrows
- May seem a bit more abstract in their notation
- Can be more efficient and flexible than Moore machine
- May require less hardware to implement
- Hardware register
- Register-transfer level (RTL)
- High-level synthesis (HLS)
- Run-time type information (RTTI)
- Digital electronics
- Electronic design automation (EDA)
- Integrated circuit (IC)
- Very Large Scale Integration (VLSI)
- Very high speed integrated circuit (VHSIC)
- Random-access memory (RAM)
- Dynamic random-access memory (DRAM)
- Robert H. Dennard 1932—2024
- Resistive random-access memory (ReRAM or RRAM)
- Reduced Latency DRAM (RLDRAM)
- Memristor
- Dual In-line Memory Module (DIMM)
- Error correction code (ECC) memory
- Error correction code (ECC)
- Hard disk drive (HDD)
- Solid-state drive (SSD)
- Hybrid drive
- Flash memory
- SD card
- Non-volatile memory (NVM)
- Read-only memory (ROM)
- Programmable read-only memory (PROM)
- Erasable programmable read-only memory (EPROM)
- Electrically erasable programmable read-only memory (EEPROM)
- Embedded system
- Firmware
- Netlist
- Hardware description language (HDL)
- Hardware verification language (HVL)
- Programmable logic controller (PLC)
- Programmable Array Logic (PAL)
- Complex programmable logic device (CPLD)
- Field-programmable gate array (FPGA)
- FPGA for Beginners: Glossary and Setup by Miranda Hansen
FPGA firmware: Though the code deployed on the FPGA is sometimes referred to as its firmware, this is a slight misconception. Firmware is indeed embedded and dedicated code, but the code is executed. FPGA code is written in a description language, then is interpreted, synthesized, and ultimately produces hardware. So, I see it fit to refer to the FPGA, when it is configured, as hardware, and to the code itself as a description language.
- Embedded FPGA (eFPGA)
- Low-voltage differential signaling (LVDS)
- Small Computer System Interface (SCSI)
- Industry Standard Architecture (ISA)
- Extended Industry Standard Architecture (EISA)
- Peripheral Component Interconnect (PCI)
- Peripheral Component Interconnect Express (PCIe)
PCIe peer-to-peer (P2P) communication is a PCIe feature that enables two PCIe devices to directly transfer data between each other without using host RAM as a temporary storage
- PCI Express Mini Card (Mini PCIe)
- Universal Chiplet Interconnect Express (UCIe)
- Serial Advanced Technology Attachment (SATA)
- M.2
- Transfers per second (T/s)
- FPGA Mezzanine Card (FMC)
- PCI Mezzanine Card (PMC)
- Multi-gigabit transceiver (MGT)
- Serializer/Deserializer (SerDes)
- Xilinx high speed serial
- SYZYGY
- Bit error rate
- FPGA for Beginners: Glossary and Setup by Miranda Hansen
- Soft microprocessor
- Application-specific integrated circuit (ASIC)
- Electromagnetic interference (EMI)
- Electromagnetic shielding
- CE marking
- Restriction of Hazardous Substances Directive (RoHS)
- Waste Electrical and Electronic Equipment Directive (WEEE)
- Hardware acceleration
- AI accelerator or neural processing unit (NPU)
- Printed circuit board (PCB)
- Fundamentals of Printed Circuit Board Technologies by American Standard Circuits
- Gerber format is named after Heinz Joseph Gerber 1924—1996
- Microstrip
- Eurocard
- Advanced Technology eXtended (ATX)
- Nano-ITX
- 19-inch rack
- Horizontal pitch (HP) is 0.2 inches (5.08 mm) used to measure the horizontal width of rack mounted electronic equipment
- Rack unit (U) is 1.75 inches (44.45 mm) used to measure vertical heights of rack mounted equipment
- Open Compute Project (OCP)
- Open Rack
- Central processing unit (CPU)
- Data processing unit (DPU)
- Graphical processing unit (GPU)
- Compute Unified Device Architecture (CUDA)
- CUDA Deep Neural Network library (cuDNN)
- AMD Accelerated Processing Unit (APU)
- Direct memory access (DMA)
- In-memory processing
- Legendre memory unit (LMU)
- Multiple buffering
- Framebuffer
- Tensor Processing Unit (TPU)
- Vision processing unit (VPU)
- Deep learning processor
- Neural processor
- Organ-on-a-chip (OOC)
- List of quantum processors
- Semiconductor intellectual property core (IP core)
- GNU Lesser General Public License (LGPL)
- CERN Open Hardware License (OHL)
- CERN OHL Version 2
- Circuit bending
- VHDL (VHSIC HDL)
- Textbook: Free Range VHDL, 2019 Edition
by Bryan Mealy and Fabrizio Tappero
Page 7: "Modeling digital circuits with VHDL is a form of modern digital design distinct from schematic-based approaches."
Page 120: "The tendency at this juncture in your VHDL programming career is to use some type of schematic capture software instead of learning the structural modeling approach. The fact is that no one of consequence uses the schematic capture software these days even though it is taught in many university textbooks. The funny part about this entire process is that the schematic capture software is a tool that allows you to visually represent circuits but in the end generates VHDL code (the only thing the synthesizer understands is VHDL code)."
Page 131: “Digital design using schematic capture is an outdated approach: you should resist the inclination and/or directive at all costs.”
Page 173: "After years of development by the US Department of Defense, in February 1986 all VHDL rights were transferred to the Institute of Electrical and Electronics Engineers (IEEE) which since then has carried on the process of standardization of the language. After several language standardization steps that took place in 1987, 1993, 2000, 2002, and 2008, VHDL now includes a large set of packages that, once included in your code, give you the possibility of using several mathematical constants, numerical functions, overloaded operators, type conversion functions, enhanced signal types, and much more."
Page 177: "This section presents the solutions to all problems presented throughout this book." - Ada programming language
- IEEE 1164-1993: IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic 1164)
- std_logic vs. std_ulogic by VHDLwhiz
- Signed vs. Unsigned in VHDL by Nandland
- IEEE 1076-2019: IEEE Standard VHDL Language Reference Manual
- VHDL GitHub repositories
- VHDL Quick Reference Cards
- VHDL Language Refernece Guide
- Overloading allows defining operators of the same names as predefined operators, but for different operand types
- Predefined attributes, e.g., CLK'event: the attribute "event" of the signal CLK followed by an apostrophe
- VHDL tutorials
- Basic VHDL Tutorials of VHDLwhiz by Jonas Julian Jensen
- FPGA Design Using VHDL Lectures of Eduvance by Jonathan Joshi and Amit Kathuria
- FPGA design with VHDL by Meher Krishna Patel of Xilinx
- SynthWorks VHDL training experts
- VHDL-Online of Chemnitz University of Technology
- VHDL Tutorial and Examples of Nandland by Russell Merrick
- VHDL Tutorial: Learn by Example by Weijun Zhang, UC Riverside, July 2001
- VHDL Tutorial by Jan Van der Spiegel, University of Pennsylvania
- VHDL reference material by UMBC CSEE
- VHDL code for flip-flops using behavioral method - full code by Umair Hussaini, Technobyte
- Verilog HDL
- SystemVerilog HDL
- IEEE 1364-2005: IEEE Standard for Verilog Hardware Description Language
- IEEE 1364-2005 was superseded by IEEE 1800-2009
- IEEE 1800-2017: IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
- Verilog Quick Reference Card
- Verilog Language Reference Guide
- SystemVerilog Language Reference Manual
- Stuart Sutherland, Verilog HDL Quick Reference Guide
- Rajeev Madhavan, Quick Reference for Verilog HDL
- Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition
- M. Morris Mano and Michael D. Ciletti, Digital Design With an Introduction to the Verilog HDL
- Pong P. Chu, FPGA Prototyping by Verilog Examples, Xilinx Spartan-3 Version
- Jayaram Bhasker Verilog HDL Synthesis: A Practical Primer
- Eduardo Corpeño, Learning FPGA Development
- ChipVerify tutorials on Verilog, SystemVerilog, and Universal Verification Methodology (UVM)
- SystemC
- SystemC.org
- IEEE 1666-2011: IEEE Standard for Standard SystemC® Language Reference Manual
- IEEE 1666.1-2016: IEEE Standard for Standard SystemC® Analog/Mixed-Signal Extensions Language Reference Manual
- C to HDL
- MyHDL Python-based HDL
- Open3D
- OpenACC (Open Accelerators)
- OpenCL (Open Computing Language)
- OpenCV (Open Source Computer Vision Library)
- OpenGL (Open Graphics Library)
- OpenMP (Open Multi-Processing)
- OpenQASM (Open Quantum Assembly Language)
- PYNQ (Python productivity for Zynq)
- PYNQ uses the Python language and libraries with AMD Xilinx Zynq, Zynq UltraScale+, Zynq MPSoC, Zynq RFSoC, Alveo accelerator boards, and Amazon EC2 F1 instances
- PYNQ introduction
- PYNQ GitHub repository
- Face Detection and Recognition by Chao Shi
- Sigasi
- XIMEA
- Synopsys
- Cadence Design Systems
- Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels
- Spectre Circuit Simulator
- Siemens EDA
- Aldec
- Altium
- GHDL
- The 17-minute tutorial plus 7-minute Q&A by Tristan Gingold at FOSDEM 2018
- Downloadable slides
- GHDL Documentation
- GHDL labs including hello_world, half adder, full adder, 8-bit square root, D flip-flop, T flip-flop, SR flip-flop, 4-to-1 multiplexer, and 1-to-4 demultiplexer
- 4-Bit Ripple Counter, 4x4 Unsigned Mulitplier, and Hamming Distance Circuit by Chloe Quinto
- Textbook Exercises of Chapters 3 to 5 and Chapters 7 to 10 by Sarah Bertussi
- Textbook Chapter 13 Test Benches by Jake Foglia
- Icarus Verilog
Daedalus warned Icarus first of complacency and then of hubris, instructing him to fly neither too low nor too high, lest the sea's dampness clog his wings or the sun's heat melt them.
- Stephen Williams
- Installation Guide
- iverilog
- Examples including hello, square-root device, configurable logic block (CLB) flip-flop, Data Encryption Standard (DES) encryptor, etc.
- ivtest
- Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer, Parallel Programming for FPGAs ArXiv e-prints, May 11, 2018, arXiv:1805.03648 [cs.AR] (PDF)
- Kastner Research Group (KRG), UC San Diego
- FPGARelated.com
- Enclustra
- FPGA Developer by Jeff Johnson
- Adam Taylor
- YouTube Channel: Adiuvo Engineering & Training
- Adiuvo is a Latin word that means “to help, assist”
- AMD Xilinx
- NI Digilent FPGA boards
- Digilent Nexys 4 DDR rebranded as Nexys A7-100T
- Double data rate (DDR)
- Reference Manuals
- Vivado ML Standard Edition by Xilinx
- Vivado installation
- Board files
- Tool command language (Tcl)
- Lab 1: Seven-Segment Decoder
- Lab 2: Four-Digit Hex Counter
- Lab 3: Bouncing Ball
- Lab 4: Hex Calculator
- Lab 5: Digital-to-Analog Converter (DAC) Siren
- Lab 6: Video Game PONG
- What’s different between Vivado and Vitis
Vivado offers a hardware-centric approach to designing hardware, while Vitis offers a software-centric approach to developing both hardware and software.
- Columbia University EE E3082 - Digital Electronics Laboratory by Prof. Ken Shepard
- Intel
- Altera
- Terasic boards
- Quartus Prime Lite Edition by Intel
- Cornell ECE 5760 Advanced Microcontroller Design and System-on-Chip Projects
- Georgia Tech ECE 2031 Digital Design Laboratory
- Terasic DE2
- DE2 Board Resources
- J. Hamblen, T. Hall, and M. Furman, Rapid Prototyping of Digital Systems, SoPC (System-on-a-Programmable Chip) Edition (PDF), 2007
- Lattice Semiconductor
- Lattice Diamond design software
- Lattice FPGAs
- STEP-MXO2 development board
- iCE FPGA
- ECP5 FPGA
- CrossLink-NX FPGA