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ports/stm32: Add support for additional GC blocks. #17019

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Merged
merged 2 commits into from
Jun 26, 2025

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iabdalkader
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@iabdalkader iabdalkader commented Mar 27, 2025

Summary

This patch adds support for defining additional GC blocks (for split heap) via linker scripts. While split GC on its own is very useful, there isn't a standard way to actually use it, so maybe this will be a step towards that.

For the Giga board, a few blocks in SDRAM/SRAM are also enabled as an example.

Testing

I tested on the Giga, checked the blocks addresses an sizes passed to gc_add and mem_free. This change is enabled conditionally when split heap is enabled, so should not have any effect on other boards as none use split heaps.

Trade-offs and Alternatives

If linker scripts were processed through CPP, we could define these blocks in board config files and make the linker script section common. Since this is not the case, this table structure will have to be duplicated if other boards want to use this. I've tried to add a common linker script (common_gc_table.ld) but without CPP it's very hard to make this generic (the conditionals supported by ld script are very basic).

Also, the blocks are defined in a particular order so that faster SRAM blocks are, hopefully, searched first. We wouldn't have to rely on this, if we had this feature: #16644

@iabdalkader iabdalkader force-pushed the add_stm32_gc_blocks branch from f72e02c to 6261a76 Compare March 27, 2025 12:55
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Code size report:

   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

@Gadgetoid
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Short term this would have made a lot of sense for PSRAM on the RP2, too, though we don't have the luxury of per-board linker scripts yet.

And additionally the linked issue relates to the wider problems with PSRAM on the RP2, a platform which exposes DMA and PIO to the end user in ways that could quickly trip them up when a buffer by chance falls into PSRAM.

@iabdalkader
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I hope we can find a way to standardize this, eventually, at least the C code in main.c could be common code, and ports could define the "gc table" in any way that works (via linker scripts, in board.c etc... However, for now I'm just trying to add more heap to the Giga as we have an app that's running out of memory and an unused 8MBytes SDRAM :)

And additionally the linked issue relates to the wider problems with PSRAM on the RP2, a platform which exposes DMA and PIO to the end user in ways that could quickly trip them up when a buffer by chance falls into PSRAM.

That's another strong case for implementing the memory map feature.

@iabdalkader
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Can we unblock this PR if the current solution is acceptable? We have a demo/example that doesn't work without this.

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@dpgeorge dpgeorge left a comment

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Sorry for the late review.

This looks fine to me, it's a reasonable solution that gets things working. In the future it can be refined/improved and generalised to other ports.

I built ARDUINO_GIGA firmware and inspected the elf to see that the _gc_blocks_table_start memory looked correct.

Add support for defining additional GC blocks via linker scripts.  A board
would need to define `_gc_blocks_table_start` and `_gc_blocks_table_end`
and within that region have pairs of (address, length) for each GC block
to add.

Signed-off-by: iabdalkader <[email protected]>
@dpgeorge dpgeorge force-pushed the add_stm32_gc_blocks branch from 6261a76 to 5c6da11 Compare June 26, 2025 02:13
@dpgeorge dpgeorge merged commit 5c6da11 into micropython:master Jun 26, 2025
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@iabdalkader iabdalkader deleted the add_stm32_gc_blocks branch June 26, 2025 06:55
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@sebromero

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3 participants