Sr Hardware Design Engineer - PCIe Interface - Hybrid

Founded in 2016 and headquartered in the San Francisco Bay Area, we are building the worlds fastest AI supercomputer meaning the smallest, fastest and greenest general-purpose chip with wide applications in hyperscale data centers, private cloud, and AI/high-performance computing.

We are actively interviewing for a Sr Hardware Design Engineer who has experience implementing, debugging, and verifying a high-performance PCIe interface including helping build the infrastructure to support PCIe during FPGA emulation and bringup.

Top Reasons to Work with Us

• Join a well funded startup having an immediate impact day 1!
• Competitive Base + Equity
• Medical, Dental, Vision, 401K
• PTO, Holidays, Remote Work, and more!
  
  

What You Will Be Doing

• Working with a small team to implement, debug, and verify a high-performance PCIe interface
• Build the infrastructure to support PCIe during FPGA emulation and bringup
  
  

What You Need for this Position

• BS in related field
• 10+ years of experience
• PCIe controller/device design
• Bus traffic analyzers and logic analyzers
• Data eye and BER analysis
• Verilog / System Verilog / Synthesis / STA / CDC / Lint experience
  
  

So if you are a Sr Hardware Design Engineer w/ PCIe Interface experience, please apply today!

Email Your Resume In Word To

Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:

[email protected]

• Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : CV5-1720408 -- in the email subject line for your application to be considered.***
  
  

Caroline Veillon - Lead Recruiter

Applicants must be authorized to work in the U.S.

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