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The Single-Chip Cloud Computer (SCC) is a computer processor created by Intel Corporation in 2009 that features 48 distinct physical cores.^[1] These cores communicate through an architecture similar to a cloud computer data center. Cores are components of the processor responsible for executing instructions that enable the computer to function. The SCC resulted from an Intel project focusing on researching multi-core processors and parallel processing. Intel also aimed to explore the integration of designs and architecture from large cloud computer data centers (cloud computing) into a single processing chip. The name "Single-chip Cloud Computer" reflects this concept.^[2]

Uses[edit]

The SCC is currently utilized for research purposes. It can run the Linux operating system on the chip but it cannot run Windows.^[3] Some applications of the SCC include web servers, data informatics, bioinformatics, and financial analytics.^[4]

Technical details[edit]

The cores are spread across the chip but capable of direct communication. The chip comprises 48 P54C Pentium cores connected with a 4×6 2D-mesh. This mesh consists of 24 tiles arranged in four rows and six columns. Each tile contains two cores and a 16 KB (8 per core) message passing buffer (MPB) shared by the two cores, essentially functioning as a router.^[5] This router enables each core to communicate directly with others, eliminating the need to send information back to the main memory for rerouting to other cores.^[3] The SCC contains 1.3 billion 45 nm transistors capable of amplifying signals or acting as a switch, using 25 to 125 watts of power depending on processing demand. Each chip includes four DDR3 memory controllers connected to the 2D mesh, capable of addressing 64 GB of random-access memory. The DDR3 memory facilitates communication among tiles, contributing to the chip's functionality. These controllers, along with the transistors, manage the activation and deactivation of specific tiles to conserve power when not in use. Proper coding integration results in a functional processor with high speed, power, and energy efficiency, resembling a network of cloud computers.^[6]

Modes of operation[edit]

The SCC comes with RCCE, a simple message-passing interface provided by Intel supporting basic message-buffering operations.^[5] The SCC operates in two modes: processor mode and mesh mode.

Processor mode[edit]

In processor mode, cores are active, executing code from the system memory, and performing programmed I/O (inputs and outputs) through the system connected to the system board FPGA. Software running on the SCC's embedded management console handles tasks such as loading memory and configuring the processor for bootstrapping (sustaining after the initial load).^[7]

Mesh mode[edit]

In mesh mode, cores are turned off, leaving only the routers, transistors, and RAM controllers active. These components send and receive large packets of data without a memory map.^[7]

The future[edit]

Intel intends to share this technology with other companies, including HP, Yahoo, and Microsoft, to foster collaborative research on the SCC to advance the technology. The goal is to make the SCC scalable to 100+ cores, potentially achieved by enabling communication between individual chips. Intel aims to enhance parallel programming productivity and power management, leveraging the chip's architecture and numerous cores. Further experimentation is planned on this architecture and similar chip architectures to develop many-core scalable processors maximizing processing power while maintaining energy efficiency.^[4]

References[edit]

^ "SCCC PDF from intel.cn" (PDF). Intel | China. Retrieved December 27, 2023.
^ Ng, Jason. "Intel Demonstrates 48-Core "Single-Chip Cloud Computer"". Daily Tech. Retrieved 30 October 2014.
^ ^a ^b Corley, Anne-Marie (9 February 2010). "Intel Lifts the Hood on its "Single-Chip Cloud Computer"". IEEE Spectrum. IEEE. Retrieved 30 October 2014.
^ ^a ^b "Intel Labs Announces Single-chip Cloud Computing Experimental Chip". YouTube. Intel. Retrieved 11 November 2014.^{[dead link]}
^ ^a ^b Pichel, Juan; Rivera, Francisco (2013). "Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor". Journal of Parallel and Distributed Computing. 73 (12): 1539–1550. doi:10.1016/j.jpdc.2013.07.017.
^ Matson, Tim. "Using Intel's Single-Chip Cloud Computer (SCC)" (PDF). Intel.com. Intel Corporation. Retrieved 30 October 2014.^{[dead link]}
^ ^a ^b Nerurkar, Nishad; Mhatre, Aniket. "Overview of the Intel Single Chip Cloud-Computer" (PDF). Retrieved 30 October 2014.^{[dead link]}

[1] "SCCC PDF from intel.cn" (PDF). Intel | China. Retrieved December 27, 2023.

[dailytech2-2] Ng, Jason. "Intel Demonstrates 48-Core "Single-Chip Cloud Computer"". Daily Tech. Retrieved 30 October 2014.

[IEEE-3] Corley, Anne-Marie (9 February 2010). "Intel Lifts the Hood on its "Single-Chip Cloud Computer"". IEEE Spectrum. IEEE. Retrieved 30 October 2014.

[youtube-4] "Intel Labs Announces Single-chip Cloud Computing Experimental Chip". YouTube. Intel. Retrieved 11 November 2014.^{[dead link]}

[SD-5] Pichel, Juan; Rivera, Francisco (2013). "Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor". Journal of Parallel and Distributed Computing. 73 (12): 1539–1550. doi:10.1016/j.jpdc.2013.07.017.

[power_point-6] Matson, Tim. "Using Intel's Single-Chip Cloud Computer (SCC)" (PDF). Intel.com. Intel Corporation. Retrieved 30 October 2014.^{[dead link]}

[RIT-7] Nerurkar, Nishad; Mhatre, Aniket. "Overview of the Intel Single Chip Cloud-Computer" (PDF). Retrieved 30 October 2014.^{[dead link]}

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+{{Multiple issues|
-{{refimprove|date= September 2014}}
+{{more citations needed|date= September 2014}}
+{{advert|date=July 2023}}
-The '''Single-Chip Cloud Computer (SCC)''' is a computer processor ([[central processing unit |CPU]]) created by [[Intel |Intel Corporation]] in 2009 that has 48 distinct physical cores that communicate through architecture similar to that of a cloud computer data center. Cores are a part of the processor that carry out instructions of code that allow the computer to run. The SCC was a product of a project started by Intel to research [[multi-core processor|multi-core processors]] and [[parallel computing |parallel processing]] (doing multiple calculations at once). Additionally Intel wanted to experiment with incorporating the designs and architecture of huge cloud computer data centers ([[Cloud computing]]) into a single processing chip. They took the aspect of cloud computing in which there are many remote servers that communicate with each other and applied it to a microprocessor. It was a new concept that Intel wanted to experiment with. The name "Single-chip Cloud Computer" originated from this concept.<ref name=dailytech>{{cite web|last1=Ng|first1=Jason|title=Intel Demonstrates 48-Core "Single-Chip Cloud Computer"|url=http://www.dailytech.com/Intel+Demonstrates+48Core+SingleChip+Cloud+Computer/article16951.htm|website=Daily Tech|accessdate=30 October 2014}}</ref> <br />
+}}
+The '''Single-Chip Cloud Computer''' ('''SCC''') is a computer processor created by [[Intel Corporation]] in 2009 that features 48 distinct physical cores.<ref>{{Cite web |title=SCCC PDF from intel.cn |url=https://www.intel.cn/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-single-chip-cloud-overview-paper.pdf |access-date=December 27, 2023 |website=Intel {{!}} China}}</ref> These cores communicate through an architecture similar to a cloud computer data center. Cores are components of the processor responsible for executing instructions that enable the computer to function. The SCC resulted from an Intel project focusing on researching [[multi-core processor]]s and [[Parallel computing|parallel processing]]. Intel also aimed to explore the integration of designs and architecture from large cloud computer data centers ([[cloud computing]]) into a single processing chip. The name "Single-chip Cloud Computer" reflects this concept.<ref name="dailytech2">{{cite web |last1=Ng |first1=Jason |title=Intel Demonstrates 48-Core "Single-Chip Cloud Computer" |url=http://www.dailytech.com/Intel+Demonstrates+48Core+SingleChip+Cloud+Computer/article16951.htm |accessdate=30 October 2014 |website=Daily Tech}}</ref>
 == Uses ==
-The SCC is currently still being used for research purposes. It currently can run a simple [[linux]] operating system on the chip but cannot boot into any operating systems ([[operating system|OS]]) like [[Windows]].<ref name=IEEE>{{cite web|last1=Corley|first1=Anne-Marie|title=Intel Lifts the Hood on its "Single-Chip Cloud Computer"|url=http://spectrum.ieee.org/semiconductors/processors/intel-lifts-the-hood-on-its-singlechip-cloud-computer|website=IEEE Spectrum|publisher=IEEE|accessdate=30 October 2014}}</ref> Some applications of the SCC are [[web servers]], [[informatics|data informatics]], [[bioinformatics]], and financial [[analysis|financial analytics]].<ref name=youtube>{{cite web|title=Intel Labs Announces Single-chip Cloud Computing Experimental Chip|url=https://www.youtube.com/watch?v=L_cXi7uyJU4|website=YouTube|publisher=Intel|accessdate=11 November 2014}}</ref>
+The SCC is currently utilized for research purposes. It can run the [[Linux]] operating system on the chip but it cannot run [[Windows]].<ref name=IEEE>{{cite web|last1=Corley|first1=Anne-Marie|title=Intel Lifts the Hood on its "Single-Chip Cloud Computer"|url=https://spectrum.ieee.org/semiconductors/processors/intel-lifts-the-hood-on-its-singlechip-cloud-computer|website=IEEE Spectrum|date=9 February 2010 |publisher=IEEE|accessdate=30 October 2014}}</ref> Some applications of the SCC include [[web servers]], [[informatics|data informatics]], [[bioinformatics]], and [[financial analysis|financial analytics]].<ref name="youtube">{{cite web |title=Intel Labs Announces Single-chip Cloud Computing Experimental Chip |url=https://www.youtube.com/watch?v=L_cXi7uyJU4 |accessdate=11 November 2014 |website=YouTube |publisher=Intel}}{{dead link|date=April 2024}}</ref>
-== Technical Details ==
+== Technical details ==
-Intel developed this new chip architecture based off of huge cloud data centers, the cores are separated across the chip but are able to directly communicate with each other.The chip contains 48 [[P54C (microprocessor)|P54C]] Pentium cores connected with a 4×6 2D-mesh. This mesh is a group of 24 tiles set up in four rows and six columns. Each tile contained 2 cores and a 16KB (8 per core) [[message passing]] buffer (MPB) shared by the two cores, essentially a router.<ref name=SD>{{cite web|last1=Pichel|first1=Juan|last2=Rivera|first2=Francisco|title=Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor|url=http://www.sciencedirect.com/science/article/pii/S074373151300155X|website=Science Direct|publisher=Journal of Parallel and Distributed Computing|accessdate=11 November 2014}}</ref> This router allows each core to communicate with each other. Previously cores had to send information back to the main memory and there it would be re-routed to other cores. <ref name=IEEE>{{cite web}}</ref> The SCC contains 1.3 billion 45 nanometer ([[nanometre |nm]]) long  [[transistor |transistors]] that can amplify signals or act as a switch and turn core pairs on and off. These transistors use anywhere from 25 to 125 [[watt |watts]] of power depending on the processing demand. For comparison the [[intel core#Core_i7 |Intel i7 processor]] uses 156 watts of power.<ref name =RIT>{{cite web|last1=Nerurkar|first1=Nishad|last2=Mhatre|first2=Aniket|title=Overview of the Intel Single Chip Cloud-Computer|url=http://meseec.ce.rit.edu/722-projects/fall2011/1-3.pdf|accessdate=30 October 2014}}</ref> Four DDR3 [[memory controller]]s are on each chip, connected to the 2D-mesh as well. These controllers are capable of addressing 64 GB of [[random access memory]]. The DDR3 memory is used to help each tile communicate with the others, without them the chip would not be functional. These controllers also work with the transistors to control when certain tiles are turned on and off to save power when not in use. When proper coding is implemented all of these pieces are put together you get a functional processor that is fast, powerful, and energy efficient with a framework resembling a network of cloud computers. <ref name="power point">{{cite web|last1=Matson|first1=Tim|title=Using Intel’s Single-Chip Cloud Computer  (SCC)|url=https://communities.intel.com/servlet/JiveServlet/previewBody/19269-102-1-22565/Using%20Intel%E2%80%99s%20Single-Chip%20Cloud%20Computer%20(SCC)%20-%20Intel,%20Mattson,%20Tutorial.pdf|website=Intel.com|publisher=Intel Corporation|accessdate=30 October 2014}}</ref> <br />
+The cores are spread across the chip but capable of direct communication. The chip comprises 48 [[P54C (microprocessor)|P54C]] Pentium cores connected with a 4×6 2D-mesh. This mesh consists of 24 tiles arranged in four rows and six columns. Each tile contains two cores and a 16 KB (8 per core) [[message passing]] buffer (MPB) shared by the two cores, essentially functioning as a router.<ref name=SD>{{cite journal |last1=Pichel |first1=Juan |last2=Rivera |first2=Francisco |title=Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor |journal=Journal of Parallel and Distributed Computing|doi=10.1016/j.jpdc.2013.07.017 |volume=73 |issue=12 |pages=1539–1550|year=2013 |url=https://zenodo.org/record/896293 }}</ref> This router enables each core to communicate directly with others, eliminating the need to send information back to the main memory for rerouting to other cores.<ref name="IEEE"/> The SCC contains 1.3 billion [[45 nm]] [[transistor]]s capable of amplifying signals or acting as a switch, using 25 to 125 [[watt]]s of power depending on processing demand. Each chip includes four DDR3 [[memory controller]]s connected to the 2D mesh, capable of addressing 64 GB of [[random-access memory]]. The DDR3 memory facilitates communication among tiles, contributing to the chip's functionality. These controllers, along with the transistors, manage the activation and deactivation of specific tiles to conserve power when not in use. Proper coding integration results in a functional processor with high speed, power, and energy efficiency, resembling a network of cloud computers.<ref name="power point">{{cite web |last1=Matson |first1=Tim |title=Using Intel's Single-Chip Cloud Computer (SCC) |url=https://communities.intel.com/servlet/JiveServlet/previewBody/19269-102-1-22565/Using%20Intel%E2%80%99s%20Single-Chip%20Cloud%20Computer%20(SCC)%20-%20Intel,%20Mattson,%20Tutorial.pdf |accessdate=30 October 2014 |website=Intel.com |publisher=Intel Corporation}}{{dead link|date=April 2024}}</ref>
-== Modes of Operation==
-The SCC comes with RCCE, a simple [[message passing interface]] provided by Intel that supports basic message buffering operations.<ref name=SD>{{cite web}}</ref> The SCC has two modes that it can operate under, processor mode and mesh mode:
-=== Processor Mode ===
+== Modes of operation==
+The SCC comes with RCCE, a simple [[message passing interface|message-passing interface]] provided by Intel supporting basic message-buffering operations.<ref name="SD"/> The SCC operates in two modes: processor mode and mesh mode.
-In processor mode cores are on and executing code from the system memory and programed I/O ([[Input/output|inputs and outputs]]) through the system which is connected to the system board [[FPGA]]. Loading memory and configuring the processor for [[bootstrapping]] (sustaining after the initial load) is currently done by software running on the SCC's management console that's embedded in the chip.<ref name=RIT>{{cite web}}</ref>
-=== Mesh Mode ===
+=== Processor mode ===
-Cores are turned off. Only the routers, transistors and RAM controllers are on and they are sending and receiving large [[network packet|packets]] of data. Additionally there is no [[memory map]]. <ref name=RIT>{{cite web}}</ref>
+In processor mode, cores are active, executing code from the system memory, and performing programmed I/O ([[Input/output|inputs and outputs]]) through the system connected to the system board [[FPGA]]. Software running on the SCC's embedded management console handles tasks such as loading memory and configuring the processor for [[bootstrapping]] (sustaining after the initial load).<ref name="RIT">{{cite web |last1=Nerurkar |first1=Nishad |last2=Mhatre |first2=Aniket |title=Overview of the Intel Single Chip Cloud-Computer |url=http://meseec.ce.rit.edu/722-projects/fall2011/1-3.pdf |accessdate=30 October 2014}}{{dead link|date=April 2024}}</ref>
-== Future ==
-Intel plans to share this technology with other companies such as [[HP]], [[Yahoo]], and [[Microsoft]] to have multiple companies researching the SCC to more efficiently and quickly advance the technology. They hope to make the SCC scalable to 100+ cores. One way they hope to achieve this is by having each chip be able to communicate with another chip, and they could put two chips together to get double the cores. They hope to improve the parallel programming productivity and power management to take advantage of the chip's architecture and large number of cores. Additionally they plan to experiment more with this architecture and similar chip architectures to develop a many-core scalable processors that maximizes the processing power of the cores while being power efficient. <ref name=youtube>{{cite web}}</ref>
+=== Mesh mode ===
+In mesh mode, cores are turned off, leaving only the routers, transistors, and RAM controllers active. These components send and receive large [[network packet|packets]] of data without a [[memory map]].<ref name="RIT"/>
+== The future ==
+Intel intends to share this technology with other companies, including [[Hewlett-Packard|HP]], [[Yahoo]], and [[Microsoft]], to foster collaborative research on the SCC to advance the technology. The goal is to make the SCC scalable to 100+ cores, potentially achieved by enabling communication between individual chips. Intel aims to enhance parallel [[programming productivity]] and power management, leveraging the chip's architecture and numerous cores. Further experimentation is planned on this architecture and similar chip architectures to develop many-core scalable processors maximizing processing power while maintaining energy efficiency.<ref name="youtube"/>
 == See also ==
-*[[Intel MIC]]
+* [[Intel MIC]]
-*[[Intel Tera-Scale]]
+* [[Intel Tera-Scale]]
-*[[Teraflops Research Chip]]
+* [[Teraflops Research Chip]]
-==References==
+== References ==
 {{Reflist}}
+{{Intel}}
 [[Category:Cloud computing]]
-[[Category:Intel Corporation]]
+[[Category:Intel]]
 [[Category:Intel microprocessors]]
+[[Category:Manycore processors]]
 [[Category:Parallel computing]]
-{{compu-eng-stub}}