90 nm process: Difference between revisions
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{{CMOS manufacturing processes}} |
{{CMOS manufacturing processes}} |
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The '''90 nanometer''' ('''90 nm''') process refers to the level of [[CMOS]] process technology that was reached by the 2003–2005 timeframe, by leading semiconductor companies like [[Toshiba]], [[Sony]], [[Samsung]], [[ |
The '''90 nanometer''' ('''90 nm''') process refers to the level of [[CMOS]] process technology that was reached by the 2003–2005 timeframe, by leading semiconductor companies like [[Toshiba]], [[Sony]], [[Samsung]], [[IBM]], [[Intel]], [[Fujitsu]], [[TSMC]], [[Elpida Memory|Elpida]], [[AMD]], [[Infineon]], [[Texas Instruments]] and [[Micron Technology]]. |
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The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. |
The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. by Toshiba, Sony and Samsung developed a 90{{nbsp}}nm process during 2001{{ndash}}2002, before being introduced in 2002 for Toshiba's [[eDRAM]] and Samsung's 2{{nbsp}}[[Gibibit|Gb]] [[NAND flash]] memory.<ref>{{cite news |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |accessdate=26 June 2019 |work=[[Toshiba]] |date=3 December 2002}}</ref><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |accessdate=25 June 2019}}</ref> IBM demonstrated a 90{{nbsp}}nm [[silicon-on-insulator]] (SOI) process, with development led by [[Ghavam Shahidi]], in 2002. The same year, Intel also demonstrated a 90{{nbsp}}nm [[strained-silicon]] process.<ref>{{cite news |title=IBM, Intel wrangle at 90 nm |url=https://www.eetimes.com/document.asp?doc_id=1145379 |accessdate=17 September 2019 |work=[[EE Times]] |date=13 December 2002}}</ref> Fujitsu commercially introduced its 90{{nbsp}}nm process in 2003<ref name="fujitsu">[http://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf 65nm CMOS Process Technology]</ref> followed by TSMC in 2004.<ref>{{cite web |title=90nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/90nm.htm |publisher=[[TSMC]] |accessdate=30 June 2019}}</ref> The naming is formally determined by the [[International Technology Roadmap for Semiconductors]] (ITRS). |
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The 193 nm wavelength was introduced by many (but not all) companies for [[photolithography|lithography]] of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new [[photoresist]]s) were reflected in the high costs associated with this transition. |
The 193 nm wavelength was introduced by many (but not all) companies for [[photolithography|lithography]] of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new [[photoresist]]s) were reflected in the high costs associated with this transition. |
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Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter. |
Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter. |
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[[Gurtej Sandhu|Gurtej Singh Sandhu]] of Micron Technology initiated the development of [[atomic layer deposition]] high-k [[Thin film|films]] for [[Dynamic random-access memory|DRAM]] memory devices. This helped drive cost-effective implementation of [[semiconductor memory]], starting with 90 |
[[Gurtej Sandhu|Gurtej Singh Sandhu]] of Micron Technology initiated the development of [[atomic layer deposition]] high-k [[Thin film|films]] for [[Dynamic random-access memory|DRAM]] memory devices. This helped drive cost-effective implementation of [[semiconductor memory]], starting with 90{{nbsp}}nm [[Semiconductor node|node]] DRAM.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |accessdate=4 July 2019}}</ref> |
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==Example: Elpida 90 nm DDR2 SDRAM process== |
==Example: Elpida 90 nm DDR2 SDRAM process== |
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Revision as of 20:42, 17 September 2019
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| Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
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Future
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The 90 nanometer (90 nm) process refers to the level of CMOS process technology that was reached by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.
The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. by Toshiba, Sony and Samsung developed a 90 nm process during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory.[1][2] IBM demonstrated a 90 nm silicon-on-insulator (SOI) process, with development led by Ghavam Shahidi, in 2002. The same year, Intel also demonstrated a 90 nm strained-silicon process.[3] Fujitsu commercially introduced its 90 nm process in 2003[4] followed by TSMC in 2004.[5] The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.
Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.
Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90 nm node DRAM.[6]
Example: Elpida 90 nm DDR2 SDRAM process
Elpida Memory's 90 nm DDR2 SDRAM process.[7]
- Use of 300 mm wafer size
- Use of KrF (248 nm) lithography with optical proximity correction
- 512 Mbit
- 1.8 V operation
- Derivative of earlier 110 nm and 100 nm processes
Processors using 90 nm process technology
- Sony/Toshiba EE+GS (PlayStation 2) - 2003[8]
- IBM PowerPC G5 970FX - 2004
- IBM PowerPC G5 970MP - 2005
- IBM PowerPC G5 970GX - 2005
- IBM "Waternoose" Xbox 360 Processor - 2005
- IBM/Sony/ Toshiba Cell Processor - 2005
- Intel Pentium 4 Prescott - 2004-02
- Intel Celeron D Prescott-256 - 2004-05
- Intel Pentium M Dothan - 2004-05
- Intel Celeron M Dothan-1024 - 2004-08
- Intel Xeon Nocona, Irwindale, Cranford, Potomac, Paxville - 2004-06
- Intel Pentium D Smithfield - 2005-05
- AMD Athlon 64 Winchester, Venice, San Diego, Orleans - 2004-10
- AMD Athlon 64 X2 Manchester, Toledo, Windsor - 2005-05
- AMD Sempron Palermo and Manila - 2004-08
- AMD Turion 64 Lancaster and Richmond - 2005-03
- NVIDIA GeForce 8800 GTS (G80) - 2006
- AMD Turion 64 X2 Taylor and Trinidad - 2006-05
- AMD Opteron Venus, Troy, and Athens - 2005-08
- AMD Dual-core Opteron Denmark, Italy, Egypt, Santa Ana, and Santa Rosa
- VIA C7 - 2005-05
- Loongson (Godson) 2Е STLS2E02 - 2007-04
- Loongson (Godson) 2F STLS2F02 - 2008-07
- MCST-4R - 2010-12
- Elbrus-2S+ - 2011-11
See also
References
- ^ "Toshiba and Sony Make Major Advances in Semiconductor Process Technologies". Toshiba. 3 December 2002. Retrieved 26 June 2019.
- ^ "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
- ^ "IBM, Intel wrangle at 90 nm". EE Times. 13 December 2002. Retrieved 17 September 2019.
- ^ 65nm CMOS Process Technology
- ^ "90nm Technology". TSMC. Retrieved 30 June 2019.
- ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
- ^ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report
- ^ "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.
External links
| Preceded by 130 nm |
CMOS manufacturing processes | Succeeded by 65 nm |
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